Cypress Semiconductor /psoc63 /GPIO /PRT[9] /INTR_CFG

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Interpret as INTR_CFG

EDGE0_SEL=DISABLE, FLT_EDGE_SEL=DISABLE

Description

Port interrupt configuration register

Fields

EDGE0_SEL	Sets which edge will trigger an IRQ for IO pin 0 0 (DISABLE): Disabled 1 (RISING): Rising edge 2 (FALLING): Falling edge 3 (BOTH): Both rising and falling edges
EDGE1_SEL	Sets which edge will trigger an IRQ for IO pin 1
EDGE2_SEL	Sets which edge will trigger an IRQ for IO pin 2
EDGE3_SEL	Sets which edge will trigger an IRQ for IO pin 3
EDGE4_SEL	Sets which edge will trigger an IRQ for IO pin 4
EDGE5_SEL	Sets which edge will trigger an IRQ for IO pin 5
EDGE6_SEL	Sets which edge will trigger an IRQ for IO pin 6
EDGE7_SEL	Sets which edge will trigger an IRQ for IO pin 7
FLT_EDGE_SEL	Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL 0 (DISABLE): Disabled 1 (RISING): Rising edge 2 (FALLING): Falling edge 3 (BOTH): Both rising and falling edges
FLT_SEL	Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.

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